器件名称: MC100E143
功能描述: 9-BIT HOLD REGISTER
文件大小: 108.12KB 共4页
简 介:MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
9Bit Hold Register
The MC10E/100E143 is a 9-bit holding register, designed with byte-parity applications in mind. The E143 holds current data or loads new data, with the nine inputs D0 – D8 accepting parallel input data.
MC10E143 MC100E143
9-BIT HOLD REGISTER
700MHz Min. Operating Frequency 9-Bit for Byte-Parity Applications Asynchronous Master Reset Dual Clocks Extended 100E VEE Range of – 4.2V to – 5.46V 75k Input Pulldown Resistors
The SEL (Select) input pin is used to switch between the two modes of operation — HOLD and LOAD. Input data is accepted by the registers a set-up time before the positive going edge of CLK1 or CLK2. A HIGH on the Master Reset pin (MR) asynchronously resets all the registers to zero. Pinout: 28-Lead PLCC (Top View)
SEL 25 MR CLK1 CLK2 VEE NC D0 D1 26 27 28 1 2 3 4 5 6 7 8 9 10 11 D8 24 D7 23 D6 22 D5 21 VCCO 20 Q8 19 18 17 16 15 14 13 12 Q7 Q6 VCC Q5 D0 VCCO Q4 Q3 D2 MUX D R Q3 R Q2 D1 MUX D R Q1 FN SUFFIX PLASTIC PACKAGE CASE 776-02
LOGIC DIAGRAM
MUX D R Q0
D2 D3 D4 VCCO Q0 Q1 Q2 * All VCC and VCCO pins are tied together on the die. D3
MUX
D
PIN NAMES
Pin D0 – D8 SEL CLK1, CLK2 MR Q0 – Q8 NC Parallel Data Inputs Mode Select Input Clock Inputs Master Reset Data Outputs No Connection Function
MUX D8 SEL CLK1 CLK2 MR
D R
Q8
FUNCTIONS
SEL L H
12/93
Mode Load Hold
Motorola, Inc. 1996
2–1
REV 2
MC10E143 MC100E143
DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = VCCO = GND)
0°C Symb……
