器件名称: MC100E142FN
功能描述: 5V ECL 9-Bit Shift Register
文件大小: 150.35KB 共8页
简 介:MC10E142, MC100E142 5V ECL 9-Bit Shift Register
Description
The MC10E/100E142 is a 9-bit shift register, designed with byte-parity applications in mind. The E142 performs serial/parallel in and serial/parallel out, shifting in one direction. The nine inputs D0 D8 accept parallel input data, while S-IN accepts serial input data. The Qn outputs do not need to be terminated for the shift operation to function. To minimize noise and power, any Q output not used should be left unterminated. The SEL (Select) input pin is used to switch between the two modes of operation SHIFT and LOAD. The shift direction is from bit 0 to bit 8. Input data is accepted by the registers a set-up time before the positive going edge of CLK1 or CLK2; shifting is also accomplished on the positive clock edge. A HIGH on the Master Reset pin (MR) asynchronously resets all the registers to zero. The 100 Series contains temperature compensation.
Features
http://onsemi.com
PLCC28 FN SUFFIX CASE 776
700 MHz Min. Shift Frequency 9-Bit for Byte-Parity Applications Asynchronous Master Reset Dual Clocks PECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V NECL Mode Operating Range: VCC = 0 V with VEE = 4.2 V to 5.7 V Internal Input 50 kW Pulldown Resistors ESD Protection: Human Body Model; > 2 kV, Machine Model; > 200 V Meets or Exceeds JEDEC Standard EIA/JESD78 IC Latchup Test Moisture Sensitivity Level: Pb = 1 PbFree = 3 For Additional Information, see Application Note AND8003/D Fla……
