器件名称: 74ALVC541
功能描述: Octal buffer/line driver; 3-state
文件大小: 83.62KB 共16页
简 介:INTEGRATED CIRCUITS
DATA SHEET
74ALVC541 Octal buffer/line driver; 3-state
Product specication File under Integrated Circuits, IC24 2002 Feb 26
Philips Semiconductors
Product specication
Octal buffer/line driver; 3-state
FEATURES Wide supply voltage range from 1.65 to 3.6 V Complies with JEDEC standard: JESD8-7 (1.65 to 1.95 V) JESD8-5 (2.3 to 2.7 V) JESD8B/JESD36 (2.7 to 3.6 V). 3.6 V tolerant inputs/outputs CMOS LOW power consumption Direct interface with TTL levels (2.7 to 3.6 V) Power-down mode Latch-up performance exceeds ≤250 mA ESD protection: 2000 V Human Body Model (JESD22-A114-A) 200 V Machine Model (JESD22-A115-A). QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C. SYMBOL tPHL/tPLH PARAMETER propagation delay inputs An to Yn CONDITIONS VCC = 1.8 V; CL = 30 pF; RL = 1 k DESCRIPTION
74ALVC541
The 74ALVC541 is a high-performance, low-power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. The 74ALVC541 is an octal non-inverting buffer/line driver with 3-state bus compatible outputs. The 3-state outputs are controlled by the output enable inputs OE0 and OE1. A HIGH on OEn causes the outputs to assume a high-impedance OFF-state.
TYPICAL 3.0 ns ns ns ns
UNIT
VCC = 2.5 V; CL = 30 pF; RL = 500 2.2 VCC = 2.7 V; CL = 50 pF; RL = 500 2.5 VCC = 3.3 V; CL = 50 pF; RL = 500 2.3 CI CI/O CPD input capacitance input/output capacitance power dissipation capacitance per buffer VCC = 3.3 V; notes 1 and 2 outputs enable outpu……
