器件名称: ATC18RHA
功能描述: Rad. Hard 0.18
文件大小: 187.04KB 共22页
简 介:Features
Comprehensive Library of Standard Logic and I/O Cells ATC18RHA Core pads Designed to Operate with VDD = 1.8V +/- 0.15V as Main Condition IO33 Pad Libraries Provide Interfaces to 3.3+/-0.3V and 2.5 +/- 0.25V Environments Memory Cells Compiled or synthesized to the Requirements of the Design EDAC Library Cold Sparing Buffers High Speed LVDS Buffers (655Mbps) PCI Buffers Predefined Die Sizes to Accommodate Standardized Packages and ESA (European Space Agency) Multi-project Wafer Services MQFP Package Up to 352 Pins (336 Signal Pins) MCGA Packages Up to 625 Pins (575 Signal Pins) ESD better than 2000V for IO33 and better than 1000V for PLL No single event latch-up below a LET threshold of 80 Mev/mg/cm at ambient temperature SEU hardened flip-flops Tested up to a total dose of 300 krads (Si) according to Mil Std 883 Test Method 1019 Quality Grades: QML-Q and QML-V with 5962-06B02, ESCC 9000
Rad. Hard 0.18 m CMOS Cell-based ASIC for Space Use ATC18RHA
Description
The ATC18RHA is fabricated on a proprietary 0.18 m, five-metal-layers CMOS process intended for use with a supply voltage of 1.8V ± 0.15V. The Atmel cell libraries and memory compilers have been designed and or characterized in order to be compatible with each other. Simulation representations exist for three types of operating conditions. They correspond to three characterization condition sets defined as follows: MIN conditions: – – – – – – – – – – TJ = -55°C – VDD (cell) = 1.95V – Process =……
