器件名称: 74LV175
功能描述: QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR
文件大小: 154.41KB 共8页
简 介:SN54LV175A, SN74LV175A QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR
SCLS400B – APRIL 1998 – REVISED OCTOBER 1998
D D D D D D D D
EPIC (Enhanced-Performance Implanted CMOS) Process Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot) > 2 V at VCC = 3.3 V, TA = 25°C Contain Four Flip-Flops With Double-Rail Outputs Applications Include: – Buffer/Storage Registers – Shift Registers – Pattern Generators Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Package Options Include Plastic Small-Outline (D, NS), Shrink Small-Outline (DB), Thin Very Small-Outline (DGV), and Thin Shrink Small-Outline (PW) Packages, Ceramic Flat (W) Packages, Chip Carriers (FK), and DIPs (J)
SN54LV175A . . . J OR W PACKAGE SN74LV175A . . . D, DB, DGV, NS, OR PW PACKAGE (TOP VIEW)
CLR 1Q 1Q 1D 2D 2Q 2Q GND
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
VCC 4Q 4Q 4D 3D 3Q 3Q CLK
SN54LV175A . . . FK PACKAGE (TOP VIEW)
1Q 1D NC 2D 2Q
1Q CLR NC VCC 4Q
4 5 6 7 8 3 2 1 20 19 18 17 16 15 14 9 10 11 12 13
4Q 4D NC 3D 3Q
description
The ’LV175A devices are quadruple D-type flip-flops designed for 2-V to 5.5-V VCC operation.
NC – No internal connection
These devices have a direct clear (CLR) input and feature complementary outputs from each flip-flop. Information at the data (D) inputs meeting the setup time requirements is transferred to the outputs on……
