器件名称: 74LV174DB
功能描述: Hex D-type flip-flop with reset; positive-edge trigger
文件大小: 121.78KB 共14页
简 介:INTEGRATED CIRCUITS
74LV174 Hex D-type flip-flop with reset; positive-edge trigger
Product specification Supersedes data of 1997 Apr 07 IC24 Data Handbook 1998 May 20
Philips Semiconductors
Philips Semiconductors
Product specification
Hex D-type flip-flop with reset; positive edge-trigger
74LV174
FEATURES
Wide operating voltage: 1.0 to 5.5V Optimized for Low Voltage applications: 1.0 to 3.6V Accepts TTL input levels between VCC = 2.7V and VCC = 3.6V Typical VOLP (output ground bounce) t 0.8V @ VCC = 3.3V, Typical VOHV (output VOH undershoot) u 2V @ VCC = 3.3V, Output capability: standard ICC category: MSI
Tamb = 25°C Tamb = 25°C
DESCRIPTION
The 74LV174 is a low–voltage Si–gate CMOS device and is pin and function compatible with the 74HC/HCT174. The 74LV174 has six edge–triggered D–type flip–flops with individual D inputs and Q outputs. The common clock (CP) and master reset (MR) inputs load and reset (clear) all flip–flops simultaneously. The register is fully edge–triggered. The state of each D input, one set–up time prior to the LOW–to–HIGH clock transition, is transferred to the corresponding output of the flip–flop. A LOW level on the MR input forces all outputs LOW, independently of clock or data inputs. The device is useful for applications requiring true outputs only and clock and master reset inputs that are common to all storage elements.
QUICK REFERENCE DATA
GND = 0V; Tamb = 25°C; tr = tf v2.5 ns SYMBOL tPHL/tPLH fmax CI CPD PARAMETER Propagation d……
