器件名称: 74LV165APW
功能描述: 8-bit parallel-in/serial-out shift register
文件大小: 102.57KB 共18页
简 介:INTEGRATED CIRCUITS
DATA SHEET
74LV165A 8-bit parallel-in/serial-out shift register
Product specication 2003 Jul 23
Philips Semiconductors
Product specication
8-bit parallel-in/serial-out shift register
FEATURES Wide supply voltage range from 2.0 to 5.5 V Complies with JEDEC standard: JESD8-5 (2.3 to 2.7 V) JESD8B/JESD36 (2.7 to 3.6 V) JESD8-1A (4.5 to 5.5 V). 5.5 V tolerant inputs/outputs CMOS LOW power consumption Direct interface with TTL levels (2.7 to 3.6 V) Power-down mode Asynchronous 8-bit parallel load Synchronous serial input Latch-up performance exceeds 250 mA ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V. DESCRIPTION The 74LV165A is a high-performance, low-power, low-voltage, Is-gate CMOS device and superior to most advanced CMOS compatible TTL families. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C. SYMBOL tPHL/tPLH PARAMETER propagation delay CE, CP to Q7, Q7 PL to Q7, Q7 D7 to Q7, Q7 fmax CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts; N = total load switching outputs; Σ(CL × VCC2 × fo) = sum of the outputs. 2. The condition is Vi = GND to VCC. 2003 Jul 23 2 maximum clock frequency input capacitance power dissipation capacitance per buffer VCC = 3.3 V; notes 1 and 2 VCC = 3.3 V; CL = 15 pF CONDITI……
