器件名称: 74ALVC374PW
功能描述: Octal D-type flip-flop positive edge-trigger
文件大小: 94.44KB 共20页
简 介:INTEGRATED CIRCUITS
DATA SHEET
74ALVC374 Octal D-type flip-flop; positive edge-trigger; 3-state
Product specication File under Integrated Circuits, IC24 2002 Feb 26
Philips Semiconductors
Product specication
Octal D-type ip-op; positive edge-trigger; 3-state
FEATURES Wide supply voltage range from 1.65 to 3.6 V Complies with JEDEC standard: JESD8-7 (1.65 to 1.95 V) JESD8-5 (2.3 to 2.7 V) JESD8B/JESD36 (2.7 to 3.6 V). 3.6 V tolerant inputs/outputs CMOS LOW power consumption Direct interface with TTL levels (2.7 to 3.6 V) Power-down mode Latch-up performance exceeds ≤250 mA ESD protection: 2000 V Human Body Model (JESD22-A 114-A) 200 V Machine Model (JESD22-A 115-A). DESCRIPTION
74ALVC374
The 74ALVC374 is a high-performance, low-power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. The 74ALVC374 is an octal D-type flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications. A clock (CP) input and an output enable (OE) input are common to all flip-flops. The eight flip-flops will store the state of their individual D-inputs that meet the set-up and hold times requirements on the LOW-to-HIGH CP transition. When OE is LOW, the contents of the eight flip-flops is available at the outputs. When OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops. The ‘374’ is functionally identical to the ‘574’……
