器件名称: 61SP6464
功能描述: 64K x 64 SYNCHRONOUS PIPELINE STATIC RAM
文件大小: 130.07KB 共19页
简 介:IS61SP6464
64K x 64 SYNCHRONOUS PIPELINE STATIC RAM
FEATURES
Fast access time: – 117, 100 MHz Internal self-timed write cycle Individual Byte Write Control and Global Write Clock controlled, registered address, data and control Pentium or linear burst sequence control using MODE input Five chip enables for simple depth expansion and address pipelining Common data inputs and data outputs Power-down control by ZZ input JEDEC 128-Pin TQFP 14mm x 20mm package Single +3.3V power supply Control pins mode upon power-up: – MODE in interleave burst mode – ZZ in normal operation mode These control pins can be connected to GNDQ or VDDQ to alter their power-up state
ISSI
JANUARY 2004
DESCRIPTION The ISSI IS61SP6464 is a high-speed, low-power synchronous
static RAM designed to provide a burstable, high-performance, secondary cache for the i486, Pentium, 680X0, and PowerPC microprocessors. It is organized as 65,536 words by 64 bits, fabricated with ISSI's advanced CMOS technology. The device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input. Write cycles are internally self-timed and are initiated by the rising edge of the clock input. Write cycles can be from one to eight bytes wide as controlled by the write control inputs. Separate byte enables allow individual bytes to be written. BW1 controls I……
