器件名称: MC14015BDT
功能描述: Dual 4-Bit Static Shift Register
文件大小: 251.65KB 共12页
简 介:MC14015B Dual 4-Bit Static Shift Register
The MC14015B dual 4–bit static shift register is constructed with MOS P–channel and N–channel enhancement mode devices in a single monolithic structure. It consists of two identical, independent 4–state serial–input/parallel–output registers. Each register has independent Clock and Reset inputs with a single serial Data input. The register states are type D master–slave flip–flops. Data is shifted from one stage to the next during the positive–going clock transition. Each register can be cleared when a high level is applied on the Reset line. These complementary MOS shift registers find primary use in buffer storage and serial–to–parallel conversion where low power dissipation and/or noise immunity is desired.
http://onsemi.com MARKING DIAGRAMS
16 PDIP–16 P SUFFIX CASE 648 MC14015BCP AWLYYWW 1 16 SOIC–16 D SUFFIX CASE 751B 1 16 TSSOP–16 DT SUFFIX CASE 948F 1 14 015B ALYW 14015B AWLYWW
Diode Protection on All Inputs Supply Voltage Range = 3.0 Vdc to 18 Vdc Logic Edge–Clocked Flip–Flop Design —
Logic state is retained indefinitely with clock level either high or low; information is transferred to the output only on the positive going edge of the clock pulse. Capable of Driving Two Low–power TTL Loads or One Low–power Schottky TTL Load Over the Rated Temperature Range.
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.)
Symbol VDD Vin, Vout Iin, Iout PD TA Tstg TL Parameter DC Supply Voltage Range Input or Output Voltage Range ……
