器件名称: M74HCT75TTR
功能描述: 4 BIT D TYPE LATCH
文件大小: 280.94KB 共9页
简 介:M74HCT75
4 BIT D TYPE LATCH
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HIGH SPEED : tPD = 21ns (TYP.) at VCC = 4.5V LOW POWER DISSIPATION: ICC =2A(MAX.) at TA=25°C COMPATIBLE WITH TTL OUTPUTS : VIH = 2V (MIN.) VIL = 0.8V (MAX) BALANCED PROPAGATION DELAYS: tPLH tPHL SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 4mA (MIN) PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 75
DIP
SOP
TSSOP
ORDER CODES
PACKAGE DIP SOP TSSOP TUBE M74HCT75B1R M74HCT75M1R T&R M74HCT75RM13TR M74HCT75TTR
DESCRIPTION The M74HCT75 is an high speed CMOS 4 BIT D TYPE LATCH fabricated with silicon gate C2MOS technology. It contains two groups of 2 bit latches controlled by an enable input (G12 or G34). These two latch groups can be used in different circuits. Each latch has Q and Q outputs (1Q - 4Q and 1Q - 4Q). The data applied to the data input is transferred to the Q and Q outputs when the enable input is taken high and the outputs will follow the data input as long as the enable input is kept high. When the
enable input is taken low, the information data applied to the data input is retained at the outputs. The M74HCT75 is designed to directly interface HSC2MOS systems with TTL and NMOS components. All inputs are equipped with protection circuits against static discharge and transient excess voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
September 2001
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M74HCT75
IINPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
PIN No 1, 4, 11, 8 2, 3, 6, 7 4 13 16, 15, 10, 9 12 5 SYMBOL 1Q to 4Q 1D to 4D G3 4 G1 2 1Q to 4Q GND VCC NA……
