器件名称: W256H
功能描述: 12 Output Buffer for 2 DDR and 3 SRAM DIMMS
文件大小: 176.34KB 共9页
简 介:W256
12 Output Buffer for 2 DDR and 3 SRAM DIMMS
Features
One input to 12 output buffer/drivers Supports up to 2 DDR DIMMs or 3 SDRAM DIMMS One additional output for feedback SMBus interface for individual output control Low skew outputs (< 100 ps) Supports 266 MHz and 333 MHz DDR SDRAM Dedicated pin for power management support Space-saving 28-pin SSOP package
Functional Description
The W256 is a 3.3V/2.5V buffer designed to distribute high-speed clocks in PC applications. The part has 12 outputs. Designers can configure these outputs to support 3 unbuffered standard SDRAM DIMMs and 2 DDR DIMMs. The W256 can be used in conjunction with the W250-02 or similar clock synthesizer for the VIA Pro 266 chipset. The W256 also includes an SMBus interface which can enable or disable each output clock. On power-up, all output clocks are enabled (internal pull-up).
Block Diagram
VDD3.5_2.5 BUF_IN DDR0T_SDRAM0 DDR0C_SDRAM1 DDR1T_SDRAM2 SDATA SCLOCK
PWR_DWN#
Pin Configuration[1]
FBOUT
SSOP Top View
FBOUT *PWR_DWN# DDR0T_SDRAM0 DDR0C_SDRAM1 VDD3.3_2.5 GND DDR1T_SDRAM2 DDR1C_SDRAM3 VDD3.3_2.5 BUF_IN GND DDR2T_SDRAM4 DDR2C_SDRAM5 VDD3.3_2.5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 SEL_DDR* DDR5T_SDRAM10 DDR5C_SDRAM11 VDD3.3_2.5 GND DDR4T_SDRAM8 DDR4C_SDRAM9 VDD3.3_2.5 GND DDR3T_SDRAM6 DDR3C_SDRAM7 GND SCLK SDATA
SMBus Decoding & Powerdown Control
DDR1C_SDRAM3 DDR2T_SDRAM4 DDR2C_SDRAM5 DDR3T_SDRAM6 DDR3C_SDRAM7 DDR4T_SDRAM8 DDR4C_SDRAM9 DDR5T_S……
