器件名称: PM7349
功能描述: Quad J2, E3 and DS-3 Framer
文件大小: 56.44KB 共2页
简 介:PMC-Sierra,Inc.
PM7349 S/UNI-4xD3F
Quad J2, E3 and DS-3 Framer
FEATURES
Quad DS-3, E3 (G.751 and G.832), and J2 framers. Each channel can be independently configured to be a DS-3, E3, or J2 Framer. Gapped transmit and receive clocks can be optionally generated for interface to devices which only need access to payload data bits. Provides programmable pseudorandom test pattern generation, detection, and analysis features. Provides integral transmit and receive HDLC controllers with 128-byte FIFO depths. Provides performance monitoring counters suitable for accumulation periods of up to 1 second. Provides an 8-bit microprocessor interface for configuration, control and status monitoring. Provides a standard five signal P1149.1 JTAG test port for boundary scan board test purposes. Low power 3.3 V CMOS technology with 5 V tolerant inputs. Available in a high density 256-pin SBGA package (27 mm x 27 mm). Requirement or the General Purpose data link. Provides frame synchronization for G.704 and NTT 6.312 Mbit/s J2 applications, alarm detection, and accumulates line code violations, framing errors, and CRC parity errors. An integral HDLC receiver is provided to terminate the data link. Provides a receive HDLC controller with a 128-byte FIFO to accumulate data link information. Provides detection of yellow alarm and loss of frame (LOF), and accumulates BIP-8 errors, framing errors and FEBE events. Provides programmable pseudorandom test-sequence detection (up to 232-1 bi……
