器件名称: PLL103-03XM
功能描述: DDR SDRAM Buffer with 4 DDR or 3 SDR/2 DDR DIMMS
文件大小: 149.35KB 共7页
简 介:Preliminary
PLL103-03
DDR SDRAM Buffer with 4 DDR or 3 SDR/2 DDR DIMMS
FEATURES
Generates 24-output buffers from one input. Supports up to 4 DDR DIMMS or 3 SDR DIMMS and 2 DDR DIMMS. Supports 266MHz DDR SDRAM. One additional output for feedback. Less than 5ns delay. Skew between any outputs is less than 100 ps. 2.5V or 3.3V Supply range. Enhanced DDR and SDRAM Output Drive selected by I2C. Available in 48 pin SSOP.
PIN CONFIGURATION
FBOUT VDD3.3_2.5 GND DDR0T_SDRAM10 DDR0C_SDRAM11 DDR1T_SDRAM0 DDR1C_SDRAM1 VDD3.3_2.5 GND DDR2T_SDRAM2 DDR2C_SDRAM3 VDD3.3_2.5 BUF_IN GND DDR3T_SDRAM4 DDR3C_SDRAM5 VDD3.3_2.5 GND DDR4T_SDRAM6 DDR4C_SDRAM7 DDR5T_SDRAM8 DDR5C_SDRAM9
DDR0T_SDRAM10
1 2 3 4 5 6 7 8
48 47 46 45 44 43 42 41
SEL_DDR VDD2.5 GND DDR11T DDR11C DDR10T DDR10C VDD2.5 GND DDR9T DDR9C VDD2.5 PD# GND DDR8T DDR8C VDD2.5 GND DDR7T DDR7C DDR6T DDR6C GND SCLK
PLL103-03
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
BLOCK DIAGRAM
VDD3.3_2.5 SDATA
SDATA SCLK
I2C Control
DDR0C_SDRAM11 DDR1T_SDRAM0 DDR1C_SDRAM1 DDR2T_SDRAM2 DDR2C_SDRAM3 DDR3T_SDRAM4 DDR3C_SDRAM5 DDR4T_SDRAM6
Note: #: Active Low
DESCRIPTIONS
The PLL103-03 is designed as a 3.3V/2.5V buffer to distribute high-speed clocks in PC applications. The device has 24 outputs. These outputs can be configured to support four unbuffered DDR (Double Data Rate) DIMMS or to support 2 unbuffered standard SDR (Single Data Rate) DIMMS and 2 DDR DIMMS. The PLL103-03 can ……
