器件名称: P502-52SC
功能描述: Low Phase Noise Divider by 2 VCXO (10MHz to 20MHz)
文件大小: 203.42KB 共5页
简 介:PLL502-52
Low Phase Noise Divider by 2 VCXO (10MHz to 20MHz)
FEATURES
Integrated voltage-controlled crystal oscillator circuitry (VCXO) (pull range 380ppm minimum). VCXO tuning range: 0V - V DD V. Uses inexpensive fundamental-mode parallel resonant crystals (from 20 to 40MHz). Integrated divider by 2: output range of 10MHz to 20MHz. 2.5V or 3.3V supply voltage. Selectable High Drive (30mA) or Standard Drive (10mA) output. Available in 8-Pin TSSOP or SOIC.
PIN CONFIGURATION
XOUT N/C VCON GND 1 2 3 4 8 7 6 5 XIN OE^ VDD CLK
Note: ^ denotes internal pull up
OUTPUT RANGE DESCRIPTION
DIVIDER FREQUENCY RANGE 10 - 20MHz OUTPUT BUFFER CMOS
PLL502-52
The PLL502-52 is a monolithic low jitter, high performance CMOS VCXO IC Die. It allows the control of the output frequency with an input voltage (VCON), using a low cost crystal. This makes the PLL502-52 ideal for a wide range of applications requiring a VCXO output in the 10MHz to 20MHz range, using a fundamental crystal ranging from 20 to 40 MHz.
÷2
BLOCK DIAGRAM
X IN XOUT
XTAL OSC V A R IC A P
C LK
OE
VCON
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 9/17/04 Page 1
PLL502-52
Low Phase Noise Divider by 2 VCXO (10MHz to 20MHz)
PIN DESCRIPTIONS
Name
XOUT N/C VCON GND CLK VDD OE XIN
Number
1 2 3 4 5 6 7 8
Type
I I P O P I I
Description
Crystal output. See Crystal Specifications on page 4. Not connected. Voltage Control input. Ground. Output clock. Power ……
