器件名称: CYW255OXC
功能描述: 200-MHz 24-Output Buffer for 4 DDR or 3 SDRAM DIMMS
文件大小: 255.89KB 共10页
简 介:W255
200-MHz 24-Output Buffer for 4 DDR or 3 SDRAM DIMMS
Features
One input to 24-output buffer/driver Supports up to 4 DDR DIMMs or 3 SDRAM DIMMS One additional output for feedback SMBus interface for individual output control Low skew outputs (< 100 ps) Supports 266-, 333-, and 400-MHz DDR SDRAM Dedicated pin for power management support Space-saving 48-pin SSOP package
Functional Description
The W255 is a 3.3V/2.5V buffer designed to distribute high-speed clocks in PC applications. The part has 24 outputs. Designers can configure these outputs to support four unbuffered DDR DIMMS or to support three unbuffered standard SDRAM DIMMs and two DDR DIMMS. The W255 can be used in conjunction with the W250 or similar clock synthesizer for the VIA Pro 266 chipset. The W255 also includes an SMBus interface which can enable or disable each output clock. On power-up, all output clocks are enabled (internal pull up).
Block Diagram
FBOUT
BUF_IN DDR0T_SDRAM10 DDR0C_SDRAM11 DDR1T_SDRAM0 DDR1C_SDRAM1 DDR2T_SDRAM2 DDR2C_SDRAM3 DDR3T_SDRAM4 DDR3C_SDRAM5 DDR4T_SDRAM6 DDR4C_SDRAM7 DDR5T_SDRAM8 DDR5C_SDRAM9 DDR6T DDR6C DDR7T DDR7C DDR8T DDR8C DDR9T DDR9C DDR10T
PWR_DWN# Power Down Control
Pin Configuration[1]
SSOP Top View
FBOUT VDD3.3_2.5 GND DDR0T_SDRAM10 DDR0C_SDRAM11 DRR1T_SDRAM0 DDR1C_SDRAM1 VDD3.3_2.5 GND DDR2T_SDRAM2 DDR2C_SDRAM3 VDD3.3_2.5 BUF_IN GND DDR3T_SDRAM4 DDR3C_SDRAM5 VDD3.3_2.5 GND DDR4T_SDRAM6 DDR4C_SDRAM7 DDR5T_SDRAM8 DDR5C_SDRAM9 VDD3.3_2.5 SDATA
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