器件名称: 74LV126PW
功能描述: Quad buffer/line driver 3-State
文件大小: 112.37KB 共12页
简 介:INTEGRATED CIRCUITS
74LV126 Quad buffer/line driver (3-State)
Product specification Supersedes data of 1997 Feb 03 IC24 Data Handbook 1998 Apr 28
Philips Semiconductors
Philips Semiconductors
Product specification
Quad buffer/line driver (3-State)
74LV126
FEATURES Wide operating voltage: 1.0 to 5.5 V Optimized for low voltage applications: 1.0 to 3.6 V Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V Typical VOLP (output ground bounce) < 0.8 V at VCC = 3.3 V,
Tamb = 25°C
DESCRIPTION
The 74LV126 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC/HCT126. The 74LV126 consists of four non-inverting buffers/line drivers with 3-state outputs. The 3-state outputs (nY) are controlled by the output enable input (nOE). A LOW at nOE causes the outputs to assume a high impedance OFF-state.
Typical VOHV (output VOH undershoot) > 2 V at VCC = 3.3 V, Tamb = 25°C Output capability: bus driver ICC category: MSI
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25°C; tr = tf ≤ 2.5 ns SYMBOL tPHL/tPLH CI CPD PARAMETER Propagation delay nA to nY Input capacitance Power dissipation capacitance per buffer VCC = 3.3 V; VI = GND to VCC1 CONDITIONS CL = 15 pF; VCC = 3.3 V TYPICAL 9 3.5 23 UNIT ns pF pF
NOTE: 1. CPD is used to determine the dynamic power dissipation (PD in W) PD = CPD × VCC2 × fi ) (CL × VCC2 × fo) where: fi = input frequency in MHz; CL = output load capacitance in pF; fo = output frequency in MHz; VCC = supply voltage in V; (CL × ……
