器件名称: 74ALVCH16843
功能描述: 18-bit bus-interface D-type latch 3-State
文件大小: 84.39KB 共12页
简 介:INTEGRATED CIRCUITS
74ALVCH16843 18-bit bus-interface D-type latch (3-State)
Product specification IC24 Data Handbook 1998 Aug 04
Philips Semiconductors
Philips Semiconductors
Product specification
18-bit bus interface D-type latch (3-State)
74ALVCH16843
FEATURES
Wide supply voltage range of 1.2V to 3.6V Complies with JEDEC standard no. 8-1A. CMOS low power consumption Direct interface with TTL levels Current drive ± 24 mA at 3.0 V MULTIBYTETM flow-through standard pin-out architecture Low inductance multiple VCC and GND pins for minimum noise
and ground bounce
PIN CONFIGURATION
1CLR 1OE 1Q0 GND 1Q1 1Q2 VCC 1Q3 1Q4 1Q5 GND 1Q6 1Q7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 1LE 1PRE 1D0 GND 1D1 1D2 VCC 1D3 1D4 1D5 GND 1D6 1D7 1D8 2D0 2D1 2D2 GND 2D3 2D4 2D5 VCC 2D6 2D7 GND 2D8 2PRE 2LE
All data inputs have bus hold Output drive capability 50 transmission lines @ 85°C
DESCRIPTION
The 74ALVCH16843 has two 9–bit D-type latch featuring separate D-type inputs for each latch and 3-State outputs for bus oriented applications. The two sections of each register are controlled independently by the latch enable (nLE), clear (nCLR), preset (nPRE) and output enable (nOE) control gates. When nOE is LOW, the data in the registers appear at the outputs. When nOE is HIGH, the outputs are in the high impedance OFF state. Operation of the nOE input does not affe……
