器件名称: 74ALVCH16823DGG
功能描述: 18-bit bus-interface D-type flip-flop with reset and enable 3-State
文件大小: 103.3KB 共12页
简 介:INTEGRATED CIRCUITS
74ALVCH16823 18-bit bus-interface D-type flip-flop with reset and enable (3-State)
Product specification IC24 Data Handbook 1998 Jul 29
Philips Semiconductors
Philips Semiconductors
Product specification
18-bit D-type flip-flop (3-State)
74ALVCH16823
FEATURES
Wide supply voltage range of 1.2V to 3.6V Complies with JEDEC standard no. 8-1A. CMOS low power consumption Direct interface with TTL levels Current drive ± 24 mA at 3.0 V Multibyteflow-through standard pin-out architecture Low inductance multiple VCC and GND pins to minimize noise and
ground bounce
DESCRIPTION
The 74ALVCH16823 is a 18-bit edge-triggered flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications. Incorporates bushold data inputs which eliminate the need for external pull-up resistors to hold unused inputs. The74ALVCH16823 consists of two sections of nine edge-triggered flip-flops. A clock (CP) input, an output-enable (OE) input, a Master reset (MR) input and a clock-enable( CE) input are provided for each total 9-bit section. With the clock-enable (CE) input LOW, the D-type flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH CP transition. Taking CE HIGH disables the clock buffer, thus latching the outputs. Taking the Master reset (MR) input LOW causes all the Q outputs to go LOW independently of the clock. When OE is LOW, the contents of th……
