器件名称: 74ALVCH16501DGGRG4
功能描述: 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS
文件大小: 297.45KB 共13页
简 介:www.ti.com
SN74ALVCH16501 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS
SCES024J – JULY 1995 – REVISED OCTOBER 2004
FEATURES
Member of the Texas Instruments Widebus Family UBT Transceiver Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, or Clocked Modes Operates From 1.65 V to 3.6 V Max tpd of 3.9 ns at 3.3 V ±24-mA Output Drive at 3.3 V Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds JESD 22 - 2000-V Human-Body Model (A114-A) - 200-V Machine Model (A115-A)
DGG OR DL PACKAGE (TOP VIEW)
DESCRIPTION/ORDERING INFORMATION
This 18-bit universal bus transceiver is designed for 1.65-V to 3.6-V VCC operation. Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLKAB. When OEAB is high, the outputs are active. When OEAB is low, the outputs are in the high-impedance state.
OEAB LEAB A1 GND A2 A3 VCC A4 A5 A6 GND A7 A8 A9 A10 A11 A12 GND A13 A14 A15 VCC A16 A17 GND A18 OEBA LEBA
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56 55 54 53 52 51 50 49……
