器件名称: 74ALVCH16500DGG
功能描述: 18-bit universal bus transceiver 3-State
文件大小: 88.45KB 共14页
简 介:INTEGRATED CIRCUITS
74ALVCH16500 18-bit universal bus transceiver (3-State)
Product specification Supersedes data of 1998 Aug 31 IC24 Data Handbook 1998 Sep 24
Philips Semiconductors
Philips Semiconductors
Product specification
18-bit universal bus transceiver (3-State)
74ALVCH16500
FEATURES
Complies with JEDEC standard no. 8-1A CMOS low power consumption Direct interface with TTL levels Current drive ± 24 mA at 3.0 V All inputs have bushold circuitry Output drive capability 50 transmission lines @ 85°C MULTIBYTETM flow-through standard pin-out architecture Low inductance multiple VCC and ground pins for minimum noise
and ground bounce
DESCRIPTION
The 74ALVCH16500 is a high-performance CMOS product. This device is an 18-bit universal transceiver featuring non-inverting 3-State bus compatible outputs in both send and receive directions. Data flow in each direction is controlled by output enable (OEAB and OEBA), latch enable (LEAB and LEBA), and clock (CPAB and CPBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is High. When LEAB is Low, the A data is latched if CPAB is held at a High or Low logic level. If LEAB is Low, the A-bus data is stored in the latch/flip-flop on the High-to-Low transition of CPAB. When OEAB is High, the outputs are active. When OEAB is Low, the outputs are in the high-impedance state. Data flow for B-to-A is similar to that of A-to-B but uses OEBA, LEBA and CPBA. The output enables are complimenta……
