器件名称: 74ALVCH162601DGG
功能描述: 18-bit universal bus transceiver with 30 ohm termination resistor; 3-state
文件大小: 90.35KB 共20页
简 介:INTEGRATED CIRCUITS
DATA SHEET
74ALVCH162601 18-bit universal bus transceiver with 30 termination resistor; 3-state
Product specication File under Integrated Circuits, IC24 1999 Oct 14
Philips Semiconductors
Product specication
18-bit universal bus transceiver with 30 termination resistor; 3-state
FEATURES Complies with JEDEC standard no. 8-1A CMOS low power consumption Direct interface with TTL levels MULTIBYTE flow-through standard pin-out architecture Low inductance multiple VCC and ground pins for minimum noise and ground bounce All data inputs have bus hold circuitry Integrated 30 termination resistors. DESCRIPTION
74ALVCH162601
The 74ALVCH162601 is an 18-bit universal transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive directions. Data flow in each direction is controlled by output enable (OEAB and OEBA), and clock (CPAB and CPBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CPAB is held at a HIGH or LOW logic level. If LEAB is LOW, the A-bus data is stored in the latch/flip-flop on the LOW-to-HIGH transition of CPAB. When OEAB is LOW, the outputs are active. When OEAB is HIGH, the outputs are in the high-impedance state. The clocks can be controlled with the clock-enable inputs (CEBA/CEAB). Data flow for B-to-A is similar to that of A-to-B but uses OEBA, LEBA and CPBA. To ensure the high-impedance state during power-down, ……
