器件名称: 74ALVC574PW
功能描述: Octal D-type flip-flop; positive edge-trigger; 3-state
文件大小: 99.17KB 共17页
简 介:74ALVC574
Octal D-type ip-op; positive edge-trigger; 3-state
Rev. 02 — 8 November 2007 Product data sheet
1. General description
The 74ALVC574 is an octal D-type ip-op featuring separate D-type inputs for each ip-op and 3-state outputs for bus-oriented applications. A clock input (CP) and an outputs enable input (OE) are common to all ip-ops. The eight ip-ops will store the state of their individual D-inputs that meet the set-up and hold times requirements on the LOW to HIGH CP transition. When pin OE is LOW, the contents of the eight ip-ops is available at the outputs. When pin OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does not affect the state of the ip-ops. The 74ALVC574 is functionally identical to the 74ALVC374, but has a different pin arrangement.
2. Features
s s s s s s s Wide supply voltage range from 1.65 V to 3.6 V 3.6 V tolerant inputs/outputs CMOS low power consumption Direct interface with TTL levels (2.7 V to 3.6 V) Power-down mode Latch-up performance exceeds 250 mA Complies with JEDEC standards: x JESD8-7 (1.65 V to 1.95 V) x JESD8-5 (2.3 V to 2.7 V) x JESD8B/JESD36 (2.7 V to 3.6 V) s ESD protection: x HBM JESD22-A114E exceeds 2000 V x MM JESD22-A115A exceeds 200 V
NXP Semiconductors
74ALVC574
Octal D-type ip-op; positive edge-trigger; 3-state
3. Ordering information
Table 1. Ordering information Package Temperature range Name 74ALVC574D 40 °C to +85 °C SO20 TSSOP20 Description plastic small outline package; 20……
