器件名称: 74ALVC573BQ
功能描述: Octal D-type transparent latch 3-state
文件大小: 108.06KB 共20页
简 介:INTEGRATED CIRCUITS
DATA SHEET
74ALVC573 Octal D-type transparent latch; 3-state
Product specication Supersedes data of 2002 Mar 01 2003 Jun 25
Philips Semiconductors
Product specication
Octal D-type transparent latch; 3-state
FEATURES Wide supply voltage range from 1.65 to 3.6 V Complies with JEDEC standards: JESD8-7 (1.65 to 1.95 V) JESD8-5 (2.3 to 2.7 V) JESD8B/JESD36 (2.7 to 3.6 V). 3.6 V tolerant inputs and outputs CMOS low power consumption Direct interface with TTL levels (2.7 to 3.6 V) Power-down mode Latch-up performance exceeds 250 mA ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V. DESCRIPTION The 74ALVC573 is a high-performance, low-power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C. SYMBOL tPHL/tPLH PARAMETER propagation delay input Dn to output Qn CONDITIONS VCC = 1.8 V; CL = 30 pF; RL = 1 k
74ALVC573
The 74ALVC573 is an octal D-type transparent latch featuring separate D-type inputs for each latch and 3-state outputs for bus oriented applications. A latch enable (LE) input and an output enable (OE) input are common to all internal latches. The 74ALVC573 consists of eight D-type transparent latches with 3-state true outputs. When LE is HIGH, data at the Dn inputs enters the latches. In this condition the latches are transparent, i.e. a latch output will change state each time its corresponding D-input changes. When……
