器件名称: 74AHC1G125DBVTE4
功能描述: SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT
文件大小: 453.96KB 共13页
简 介:SCLS377J AUGUST 1997 REVISED JUNE 2005
SN74AHC1G125 SINGLE BUS BUFFER GATE WITH 3STATE OUTPUT
D Operating Range of 2 V to 5.5 V D Max tpd of 6 ns at 5 V
DBV PACKAGE (TOP VIEW)
D Low Power Consumption, 10-A Max ICC D ±8-mA Output Drive at 5 V
DCK PACKAGE (TOP VIEW) DRL PACKAGE (TOP VIEW)
OE OE A GND
1 5
1 2 3
5
VCC A GND
4
VCC
OE A
1 2 3
5
VCC Y
2
Y
GND
4
3
4
Y
See mechanical drawings for dimensions.
description/ordering information
The SN74AHC1G125 is a single bus buffer gate/line driver with 3-state output. The output is disabled when the output-enable (OE) input is high. When OE is low, true data is passed from the A input to the Y output. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. ORDERING INFORMATION
TA PACKAGE Reel of 3000 SOT (SOT-23) DBV 40°C to 85°C SOT (SC-70) DCK SOT (SOT-553) DRL Reel of 250 Reel of 3000 Reel of 250 Reel of 4000 ORDERABLE PART NUMBER SN74AHC1G125DBVR SN74AHC1G125DBVT SN74AHC1G125DCKR SN74AHC1G125DCKT SN74AHC1G125DRLR AM_ AM_ A25_ TOP-SIDE MARKING
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. The actual top-side marking has one additional character that designates the assembly/test site. FUNCTION TABLE INPUTS OE L L H A H L X OUTPUT Y H L Z
logic diagram (p……
