器件名称: 74AHC126PWDH
功能描述: Quad buffer/line driver; 3-state
文件大小: 78.05KB 共16页
简 介:INTEGRATED CIRCUITS
DATA SHEET
74AHC126; 74AHCT126 Quad buffer/line driver; 3-state
Product specication Supersedes data of 1999 Jan 12 File under Integrated Circuits, IC06 1999 Sep 29
Philips Semiconductors
Product specication
Quad buffer/line driver; 3-state
FEATURES ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V CDM EIA/JESD22-C101 exceeds 1000 V Balanced propagation delays All inputs have Schmitt-trigger actions Inputs accepts voltages higher than VCC For AHC only: operates with CMOS input levels For AHCT only: operates with TTL input levels Specified from 40 to +85 and +125 °C. DESCRIPTION The 74AHC/AHCT126 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A. The 74AHC/AHCT126 are four non-inverting buffer/line drivers with 3-state outputs. The 3-state outputs (nY) are controlled by the output enable input (nOE) A LOW at nOE causes the outputs to assume a HIGH-impedance OFF state. The ‘126’ is identical to the ‘125’ but has active HIGH enable inputs. Note 1. H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF state. FUNCTION TABLE See note 1. INPUTS nOE H H L
74AHC126; 74AHCT126
OUTPUT nA L H X nY L H Z
QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf ≤ 3.0 ns. TYPICAL SYMBOL tPHL/tPLH CI CO CPD PARAMETER propagation delay nA to nY input capacitance output capacitance power d……
