器件名称: 54ACT11010
功能描述: TRIPLE 3-INPUT POSITIVE-NAND GATES
文件大小: 67.18KB 共5页
简 介:54ACT11010, 74ACT11010 TRIPLE 3-INPUT POSITIVE-NAND GATES
SCAS018A – D2957, JULY 1987 – REVISED APRIL 1993
Inputs Are TTL-Voltage Compatible Flow-Through Architecture to Optimize PCB Layout Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPIC t (Enhanced-Performance Implanted CMOS) 1-mm Process 500-mA Typical Latch-Up Immunity at 125°C Package Options Include Plastic Small-Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs
54ACT11010 . . . J PACKAGE 74ACT11010 . . . D OR N PACKAGE (TOP VIEW)
1A 1Y 2Y GND GND 3Y 3C 3B
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
1B 1C 2A VCC VCC 2B 2C 3A
description
These devices contain three independent 3-input NAND gates. They perform the Boolean functions Y = ASBSC or Y = A + B + C in positive logic. The 54ACT11010 is characterized for operation over the full military temperature range of – 55°C to 125°C. The 74ACT11010 is characterized for operation from – 40°C to 85°C.
FUNCTION TABLE INPUTS A H L X X B H X L X C H X X L OUTPUT Y L H H H
54ACT11010 . . . FK PACKAGE (TOP VIEW)
1C 1B NC 1A 1Y
4 5 6 7 8
3 2 1 20 19 18 17 16 15 14 9 10 11 12 13
2A VCC NC VCC 2B 2C 3A NC 3B 3C
NC – No internal connection
logic diagram (positive logic)
1A 1B 1C 2A 2B 2C 3A 3B 3C 2Y 1 16 15 14 11 10 9 8 7 2 1Y
logic symbol
1A 1B 1C 2A 2B 2C 3A 3B 3C 1 16 15 14 11 10 9 8 7 6 3Y 3 & 2 1Y
2Y GND NC GND 3Y
3
(each gate)
2Y
6
3Y
This symbol is in accordance with ANSI/IEEE Std 91-1984 ……