器件名称: AS7C251MPFD36A-133TQIN
功能描述: 2.5V 1M x 32/36 pipelined burst synchronous SRAM
文件大小: 522.92KB 共19页
简 介:February 2005
AS7C251MPFD32A AS7C251MPFD36A
2.5V 1M × 32/36 pipelined burst synchronous SRAM
Features
Organization: 1,048,576 words × 32 or 36 bits Fast clock speeds to 200 MHz Fast clock to data access: 3.1/3.5/3.8 ns Fast OE access time: 3.1/3.5/3.8 ns Fully synchronous register-to-register operation Double-cycle deselect Asynchronous output enable control Available in 100-pin TQFP package Individual byte write and global write Multiple chip enables for easy expansion 2.5V core power supply Linear or interleaved burst control Snooze mode for reduced power-standby Common data inputs and data outputs
Logic block diagram
LBO CLK ADV ADSC ADSP A[19:0] 20 CLK CE CLR Q0 Burst logic Q1
2 2
D Q CE Address register CLK D DQd Q Byte write registers CLK D DQ Q c Byte write registers CLK D DQb Q Byte write registers CLK D DQa Q Byte write registers CLK D Enable CE register CLK Q
1M × 32/36 Memory array
20
18
20 32/36 32/36
GWE BWE BWd
BWc
BWb
BWa CE0 CE1 CE2
4
OE Output registers CLK
Input registers CLK
ZZ
Power down
D Enable Q delay register CLK 32/36 DQ[a:d]
OE
Selection guide
Minimum cycle time Maximum clock frequency Maximum clock access time Maximum operating current Maximum standby current Maximum CMOS standby current (DC) -200 5 200 3.1 450 170 90 -166 6 166 3.5 400 150 90 -133 7.5 133 3.8 350 140 90 Units ns MHz ns mA mA mA
2/11/05, v.1.1
Alliance Semiconductor
1 of 19
Copyright Alliance Semiconductor. All rights reserved.
AS7C251MPFD32A……
