器件名称: AS7C251MNTD36A-200TQC
功能描述: 2.5V 1M x 32/36 Pipelined SRAM with NTD
文件大小: 436.16KB 共18页
简 介:January 2005
AS7C251MNTD32A AS7C251MNTD36A
2.5V 1M × 32/36 Pipelined SRAM with NTDTM
Features Organization: 1,048,576 words × 32 or 36 bits NTDarchitecture for efficient bus operation Fast clock speeds to 200 MHz Fast clock to data access: 3.2/3.5/3.8 ns Fast OE access time: 3.2/3.5/3.8 ns Fully synchronous operation pipelined mode Common data inputs and data outputs Asynchronous output enable control Logic block diagram
A[19:0] 20 D
Available in 100-pin TQFP packages Byte write enables Clock enable for operation hold Multiple chip enables for easy expansion 2.5V core power supply Self-timed write cycles Interleaved or linear burst modes Snooze mode for standby operation
Address register Burst logic
Q
20
CLK CE0 CE1 CE2 R/W BWa BWb BWc BWd ADV / LD LBO ZZ
D
Q 20
Write delay addr. registers
CLK
Control logic
CLK
Write Buffer
CLK
1M x 32/36 SRAM Array
DQ[a,b,c,d]
32/36
D
Data Q Input Register
CLK
32/36 32/36 32/36
32/36 CLK CEN CLK OE
Output Register
32/36 OE
DQ[a,b,c,d]
Selection guide
-200 Minimum cycle time Maximum clock frequency Maximum clock access time Maximum operating current Maximum standby current Maximum CMOS standby current (DC)
1/17/05, V 1.2
-166 6 166 3.5 400 150 90
-133 7.5 133 3.8 350 140 90
Units ns MHz ns mA mA mA
P. 1 of 18
5 200 3.2 450 170 90
Alliance Semiconductor
Copyright Alliance Semiconductor. All rights reserved.
AS7C251MNTD32A AS7C251MNTD36A
2.5V 32 Mb Synchronous SRAM products list1,2
Org 2MX18……
