器件名称: AS6VA25616-BI
功能描述: 2.7V to 3.3V 256K x 16 Intelliwatt low-power CMOS SRAM with one chip enable
文件大小: 180.39KB 共9页
简 介:October 2000
AS6VA25616
2.7V to 3.3V 256K × 16 Intelliwatt low-power CMOS SRAM with one chip enable Features
AS6VA25616 Intelliwatt active power circuitry Industrial and commercial temperature ranges available Organization: 262,144 words × 16 bits 2.7V to 3.3V at 55 ns Low power consumption: ACTIVE
- 132 mW at 3.3V and 55 ns
1.2V data retention Equal access and cycle times Easy memory expansion with CS, OE inputs Smallest footprint packages ESD protection ≥ 2000 volts Latch-up current ≥ 200 mA
- 48-ball FBGA - 400-mil 44-pin TSOP II
Low power consumption: STANDBY
- 66 W max at 3.3V
Logic block diagram
A0 A1 A2 A3 A4 A6 A7 A8 A12 A13 I/O1–I/O8 I/O9–I/O16 WE Row Decoder VCC 256K × 16 Array (4,194,304) VSS
Pin arrangement (top view)
44-pin 400-mil TSOP II 44 A4 1 A5 A6 43 A3 2 A2 A7 42 3 OE 41 A1 4 A0 5 UB 40 CS 6 39 LB I/O16 7 38 I/O1 I/O15 8 37 I/O2 I/O14 9 36 I/O3 I/O13 10 35 I/O4 VCC VSS 11 34 VSS VCC 12 33 13 32 I/O5 I/O12 14 31 I/O6 I/O11 15 30 I/O7 I/O10 I/O8 16 29 I/O9 17 28 WE NC 18 A17 27 A8 19 26 A9 A16 20 25 A15 A10 24 A11 A14 21 23 A12 A13 22
I/O buffer
Control circuit Column decoder A5 A9 A10 A11 A14 A15 A16 A17
UB OE LB CS
48-CSP Ball-Grid-Array Package
A B C D E F G H
1 LB I/O9 I/O10 VSS VCC I/O15 I/O16 NC
2 OE UB I/O11 I/O12 I/O13 I/O14 NC A8
3 A0 A3 A5 A17 NC A14 A12 A9
4 A1 A4 A6 A7 A16 A15 A13 A10
5 A2 CS I/O2 I/O4 I/O5 I/O6 WE A11
6 NC I/O1 I/O3 VCC V SS I/O7 I/O8 NC
Selection guide
VCC Range Product AS6VA25616 Min (V) 2.7 Typ……
