器件名称: 74LV02PW
功能描述: Quad 2-input NOR gate
文件大小: 114.69KB 共10页
简 介:INTEGRATED CIRCUITS
74LV02 Quad 2-input NOR gate
Product specification Supersedes data of 1997 Feb 03 IC24 Data Handbook 1998 Apr 20
Philips Semiconductors
Philips Semiconductors
Product specification
Quad 2-input NOR gate
74LV02
FEATURES
Wide operating voltage: 1.0 to 5.5 V Optimized for low voltage applications: 1.0 to 5.5 V Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V Typical VOLP (output ground bounce) < 0.8 V at VCC = 3.3 V, Typical VOHV (output VOH undershoot) > 2 V at VCC = 3.3 V, Output capability: standard ICC category: SSI
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25°C; tr = tf ≤ 2.5 ns SYMBOL tPHL/tPLH CI CPD PARAMETER Propagation delay nA, nB to nY Input capacitance Power dissipation capacitance per gate Tamb = 25°C Tamb = 25°C
DESCRIPTION
The 74LV02 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC/HCT02. The 74LV02 provides the 2-input NOR function.
CONDITIONS CL = 15 pF; VCC = 3.3 V See Notes 1 and 2
TYPICAL 6 3.5 22
UNIT ns pF pF
NOTES: 1. CPD is used to determine the dynamic power dissipation (PD in W) PD = CPD × VCC2 × fi ) (CL VCC2 fo) where: fi = input frequency in MHz; CL = output load capacitance in pF; fo = output frequency in MHz; VCC = supply voltage in V; VCC2 fo) = sum of the outputs. (CL 2. The condition is VI = GND to VCC.
ORDERING INFORMATION
PACKAGES 14-Pin Plastic DIL 14-Pin Plastic SO 14-Pin Plastic SSOP Type II 14-Pin Plastic TSSOP Type I TEMPERATURE RANGE –40°C to +125°C –4……
