器件名称: 74LV00A
功能描述: QUADRUPLE 2 INPUT POSITIVE NAND GATES
文件大小: 409.39KB 共14页
简 介:SN54LV00A, SN74LV00A QUADRUPLE 2INPUT POSITIVENAND GATES
SCLS389J SEPTEMBER 1997 REVISED APRIL 2005
D 2-V to 5.5-V VCC Operation D Max tpd of 6.5 ns at 5 V D Typical VOLP (Output Ground Bounce) D D
D Ioff Supports Partial-Power-Down Mode D D
Operation Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds JESD 22 2000-V Human-Body Model (A114-A) 200-V Machine Model (A115-A) 1000-V Charged-Device Model (C101)
SN54LV00A . . . FK PACKAGE (TOP VIEW)
<0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot) >2.3 V at VCC = 3.3 V, TA = 25°C Support Mixed-Mode Voltage Operation on All Ports
1A 1B 1Y 2A 2B 2Y GND
1 2 3 4 5 6 7
14 13 12 11 10 9 8
VCC 4B 4A 4Y 3B 3A 3Y
1A
1
14 13 4B 12 4A 11 4Y 10 3B 9 3A
VCC
1B 1Y 2A 2B 2Y
2 3 4 5 6 7 8
1Y NC 2A NC 2B
4 5 6 7 8
3 2 1 20 19 18 17 16 15 14 9 10 11 12 13
1B 1A NC VCC 4B 4A NC 4Y NC 3B
NC No internal connection ORDERABLE PART NUMBER TOP-SIDE MARKING LV00A LV00A 74LV00A LV00A LV00A LV00A SNJ54LV00AJ SNJ54LV00AW
Copyright 2005, Texas Instruments Incorporated
SN54LV00A . . . J OR W PACKAGE SN74LV00A . . . D, DB, DGV, NS, OR PW PACKAGE (TOP VIEW)
SN74LV00A . . . RGY PACKAGE (TOP VIEW)
GND
description/ordering information
These quadruple 2-input positive-NAND gates are designed for 2-V to 5.5-V VCC operation. The ’LV00A devices perform the Boolean function Y = A B or Y = A + B in positive logic. ORDERING INFORMATION
TA PACKAGE QFN RGY SOIC D SOP NS 40°C to 85°C SSOP DB Reel of 1000 T……