器件名称: 54ACT11000
功能描述: QUADRUPLE 2-INPUT POSITIVE-NAND GATES
文件大小: 67.64KB 共5页
简 介:54ACT11000, 74ACT11000 QUADRUPLE 2-INPUT POSITIVE-NAND GATES
SCAS002A – D2957, JUNE 1987 – REVISED APRIL 1993
Inputs Are TTL-Voltage Compatible Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPICt (Enhanced-Performance Implanted CMOS) 1-mm Process 500-mA Typical Latch-Up Immunity at 125°C Package Options Include Plastic Small-Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs
54ACT11000 . . . J PACKAGE 74ACT11000 . . . D OR N PACKAGE (TOP VIEW)
1A 1Y 2Y GND GND 3Y 4Y 4B
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
1B 2A 2B VCC VCC 3A 3B 4A
description
These devices contain four independent 2-input NAND gates. They perform the Boolean functions Y = ASB or Y = A + B in positive logic. The 54ACT11000 is characterized for operation over the full military temperature range of – 55°C to 125°C. The 74ACT11000 is characterized for operation from – 40°C to 85°C.
FUNCTION TABLE (each gate) INPUTS A H L X B H X L OUTPUT Y L H H
54ACT11000 . . . FK PACKAGE (TOP VIEW)
2A 1B NC 1A 1Y
4 5 6 7 8
3 2 1 20 19 18 17 16 15 14 9 10 11 12 13
2B VCC NC VCC 3A 3B 4A NC 4B 4Y
NC – No internal connection
logic symbol
1A 1B 2A 2B 3A 3B 4A 4B 1 16 15 14 11 10 9 8 & 2 1Y
logic diagram (positive logic)
1A 1B 2A 2Y 2B 3A 3B 7 4Y 4A 4B 4Y 3Y 2Y 1Y
3
6
3Y
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, J, and N p……