器件名称: 256M4
功能描述: 1Gb: x4, x8, x16 DDR3 SDRAM
文件大小: 8335.62KB 共181页
简 介:1Gb: x4, x8, x16 DDR3 SDRAM Features
DDR3 SDRAM
MT41J256M4 – 32 Meg x 4 x 8 Banks MT41J128M8 – 16 Meg x 8 x 8 Banks MT41J64M16 – 8 Meg x 16 x 8 Banks Features
VDD = VDDQ = +1.5V ±0.075V 1.5V center-terminated push/pull I/O Differential bidirectional data strobe 8n-bit prefetch architecture Differential clock inputs (CK, CK#) 8 internal banks Nominal and dynamic on-die termination (ODT) for data, strobe, and mask signals CAS (READ) latency (CL): 5, 6, 7, 8, 9, 10, or 11 POSTED CAS ADDITIVE latency (AL): 0, CL - 1, CL - 2 CAS (WRITE) latency (CWL): 5, 6, 7, 8, based on tCK Fixed burst length (BL) of 8 and burst chop (BC) of 4 (via the mode register set [MRS]) Selectable BC4 or BL8 on-the-fly (OTF) Self refresh mode TC of 0oC to 95oC – 64ms, 8,192 cycle refresh at 0oC to 85oC – 32ms at 85oC to 95oC Clock frequency range of 300–800 MHz Self refresh temperature (SRT) Automatic self refresh (ASR) Write leveling Multipurpose register Output driver calibration Key Timing Parameters
Data Rate (MT/s) 1600 1600 1600 1333 1333 1333 1066 1066 800 800 Target tRCD-tRP-CL 11-11-11 10-10-10 9-9-9 10-10-10 9-9-9 8-8-8 8-8-8 7-7-7 6-6-6 5-5-5
tRCD
Options
Configuration – 256 Meg x 4 – 128 Meg x 8 – 64 Meg x 16 FBGA package (Pb-free) - x4, x8 – 78-ball FBGA (8mm x 11.5mm) Rev. F – 78-ball FBGA (9mm x 11.5mm) Rev. D – 86-ball FBGA (9mm x 15.5mm) Rev. B FBGA package (Pb-free) - x16 – 96-ball FBGA (9mm x 15.5mm) Rev. B Timing - cycle time – 1.25ns @ CL = 11 (DDR3-1600) – 1.25ns ……
