器件名称: AD9554
功能描述: AD9554时钟转换器的高集成度、自适应式时钟功能以及DPLL中嵌入的光纤传输网络(OTN)映射算法，可简化时钟电路、消除软件控制例程，从而降低系统成本。在50 kHz至80 MHz范围内，输出抖动为250 fs，12 kHz至20 MHz范围内则为350 fs。
文件大小: 1639.05KB 共112页
简 介:Data Sheet
FEATURES
Quad PLL, Quad Input, Multiservice Line Card Adaptive Clock Translator AD9554
APPLICATIONS
Network synchronization, including synchronous Ethernet and synchronous digital hierarchy (SDH) to optical transport network (OTN) mapping/demapping Cleanup of reference clock jitter SONET/SDH clocks up to OC-192, including FEC Stratum 3 holdover, jitter cleanup, and phase transient control Cable infrastructure Data communications
Supports GR-1244 Stratum 3 stability in holdover mode Supports smooth reference switchover with virtually no disturbance on output phase Supports Telcordia GR-253 jitter generation, transfer, and tolerance for SONET/SDH up to OC-192 systems Supports ITU-T G.8262 synchronous Ethernet slave clocks Supports ITU-T G.823, ITU-T G.824, ITU-T G.825, and ITU-T G.8261 Auto/manual holdover and reference switchover Adaptive clocking allows dynamic adjustment of feedback dividers for use in OTN mapping/demapping applications Quad digital phase-locked loop (DPLL) architecture with four reference inputs (single-ended or differential) 4 × 4 crosspoint allows any reference input to drive any PLL Input reference frequencies from 2 kHz to 1000 MHz Reference validation and frequency monitoring: 2 ppm Programmable input reference switchover priority 20-bit programmable input reference divider 8 differential clock outputs with each differential pair configurable as HCSL, LVDS-compatible, or LVPECLcompatible Output frequency range: 430 kHz to 941 MHz Programma……
