器件名称: IDT6T39007A
功能描述: CLOCK DISTRIBUTION CIRCUIT
文件大小: 282.93KB 共15页
简 介:DATASHEET
CLOCK DISTRIBUTION CIRCUIT Description
The IDT6T39007A is a low-power, four output clock distribution circuit. The device takes a TCXO or 1.8 V to 2.5 V LVCMOS input and generates four high-quality LVDS outputs, and two programmable divided outputs. It includes a redundant input with automatic glitch-free switching when the primary reference is removed. The primary input may be selected by the user by pulling the SEL pin low or high. If the primary input is removed and brought back, it will not be re-selected until 1024 cycles have passed. The IDT6T39007A specifically addresses the needs of handheld applications in both performance and package size. The device is packaged in a small 4mm x 4mm 24-pin QFN, allowing optimal use for limited board space.
IDT6T39007A Features
Packaged in 24-pin QFN TCXO sine wave input +2.5 V operating voltage Four buffered LVDS outputs Two programmable outputs for power control up to 3.0 V LVCMOS levels based on VDDO1/VDDO2
Individual output enables controlled via I2C or OEx Pb-free, RoHS compliant package Industrial temperature range (-40°C to +85°C)
Block Diagram
VDD 2.5 V 3 SEL SCLK SDATA LVCMOS_INB OE1 OUT1 LVDS OE2 OUT2 LVDS OUT3 LVDS OUT4 LVDS VDDO1 PWRCTRL_CLK1 VDDO2 PWRCTRL_CLK2
TCXO_INA ±100mVpp
MUX Divide Logic
2 GND
IDT CLOCK DISTRIBUTION CIRCUIT
1
IDT6T39007A REV G 111009
IDT6T39007A CLOCK DISTRIBUTION CIRCUIT
DISTRIBUTION CIRCUITS
Pin Assignment
TCXO_INA SEL LVCMOS_INB
SEL Pin Configuration Table
SEL
0
……
