器件名称: CY2SSTU877BVXI-32
功能描述: 1.8V, 500-MHz, 10-Output JEDEC-Compliant Zero Delay Buffer
文件大小: 196.49KB 共9页
简 介:PRELIMINARY
CY2SSTU877
1.8V, 500-MHz, 10-Output JEDEC-Compliant Zero Delay Buffer
Features
Operating frequency: 125 MHz to 500 MHz Supports DDRII SDRAM 1 to 10 differential clock buffer (SSTL_18) Spread-Spectrum-compatible Low jitter (cycle-to-cycle): 40 ps Very low output-to-output skew: 40 ps Auto power-down feature when input is low 1.8V operation Fully JEDEC-compliant (JESD 82-8) 52-ball BGA distributes a differential clock input pair (CK, CK#) to ten differential pair of clock outputs (Y[0:9], Y#[0:9]) and one differential pair of feedback clock outputs (FBOUT, FBOUT#). The input clocks (CK, CK#), the feedback clocks (FBIN, FBIN#), the LVCMOS (OE, OS), and the analog power input (AVDD) control the clock outputs. The PLL in the CY2SSTU877 clock driver uses the input clocks (CK, CK#) and the feedback clocks (FBIN, FBIN#) to provide high-performance, low-skew, low-jitter output differential clocks (Y[0:9], Y#[0:9]). The CY2SSTU877 is also able to track Spread Spectrum Clocking (SSC) for reduced EMI. When AVDD is grounded, the PLL is turned off and bypassed for test purposes. When both clock signals (CK, CK#) are logic low, the device will enter a low-power mode. An input logic detection circuit on the differential inputs, independent from the input buffers, will detect the logic low level and perform a low-power state where all outputs, the feedback, and the PLL are OFF. When the inputs transition from both being logic low to being differential signals, the PLL ……
