器件名称: ACDM-35G
功能描述: ACDM Series Advanced CMOS Logic Buffered 5-Tap Delay Modules
文件大小: 36.41KB 共1页
简 介:ACDM Series Advanced CMOS Logic Buffered 5-Tap Delay Modules
74ACT type input is compatible with TTL
Low Profile 14-Pin Package Two Surface Mount Versions Available in Low Voltage CMOS 74LVC Logic version LVIDM Series 5 Equal Delay Taps Operating Temp. -40OC to +85OC
Outputs can Source / Sink 24 mA
Electrical Specifications at 25OC Tap Delay Tolerances +/- 5% or 2ns (+/- 1ns <13ns) 74ACT 5 Tap 14-pin DIP P/N Tap 1 Tap 2 Tap 3 Tap 4 Total - Tap 5 ACDM-30 ACDM-35 ACDM-40 ACDM-50 ACDM-60 ACDM-75 ACDM-80 ACDM-100 ACDM-125 ACDM-150 ACDM-200 ACDM-250 6.0 7.0 8.0 10.0 12.0 15.0 16.0 20.0 25.0 30.0 40.0 50.0 12.0 14.0 16.0 20.0 24.0 30.0 32.0 40.0 50.0 60.0 80.0 100.0 18.0 21.0 24.0 30.0 36.0 45.0 48.0 60.0 75.0 90.0 120.0 150.0 24.0 28.0 32.0 40.0 48.0 60.0 64.0 80.0 100.0 120.0 160.0 200.0 30 ± 2.0 35 ± 2.0 40 ± 2.0 50 ± 2.5 60 ± 3.0 75 ± 3.75 80 ± 4.0 100 ± 5.0 125 ± 6.25 150 ± 7.5 200 ± 10.0 250 ± 12.5
Tap-to-Tap (ns)
ACDM 14-Pin Schematic
Vcc 14 Tap1 12 Tap3 10 Tap5 8
6 ± 2.0 7 ± 2.0 8 ± 2.0 10 ± 2.0 12 ± 2.0 15 ± 2.5 16 ± 3.0 20 ± 3.0 25 ± 3.0 30 ± 3.0 40 ± 4.0 50 ± 5.0
1 IN
4 Tap2
6 Tap4
7 GND
Dimensions in Inches (mm)
TEST CONDITIONS -- Advanced CMOS, 74ACT
VCC Supply Voltage ................................................ 5.00VDC Input Pulse Voltage ................................................... 3.00V Input Pulse Rise Time ....................................... 3.0 ns max. Input Pulse Width / Period ........................... 1000 / 2000 ns 1. Measurements……
