器件名称: 74ALVCH16835DGGRG4
功能描述: 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS
文件大小: 487.24KB 共17页
简 介:www.ti.com
SN74ALVCH16835 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS
SCES053J – SEPTEMBER 1995 – REVISED OCTOBER 2004
FEATURES
Member of the Texas Instruments Widebus Family Operates From 1.65 V to 3.6 V Max tpd of 3.6 ns at 3.3 V ±24-mA Output Drive at 3.3 V Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds JESD 22 - 2000-V Human-Body Model (A114-A) - 200-V Machine Model (A115-A)
DGG, DGV, OR DL PACKAGE (TOP VIEW)
DESCRIPTION/ORDERING INFORMATION
This 18-bit universal bus driver is designed for 1.65-V to 3.6-V VCC operation. Data flow from A to Y is controlled by the output-enable (OE) input. The device operates in the transparent mode when the latch-enable (LE) input is high. The A data is latched if the clock (CLK) input is held at a high or low logic level. If LE is low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLK. When OE is high, the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.
NC NC Y1 GND Y2 Y3 VCC Y4 Y5 Y6 GND Y7 Y8 Y9 Y10 Y11 Y12 GND Y13 Y1……
