器件名称: CY2SSTU32866BFXC
功能描述: 1.8V, 25-bit (1:1) of 14-bit (1:2) JEDEC-Compliant Data Register with Parity
文件大小: 235.68KB 共24页
简 介:CY2SSTU32866
1.8V, 25-bit (1:1) or 14-bit (1:2) JEDEC-Compliant Data Register with Parity
Features
Operating frequency: DC to 500 MHz Supports DDRII SDRAM Two operations modes: 25 bit (1:1) and 14 bit (1:2) 1.8V operation Fully JEDEC-compliant (JESD 82-10) 96-ball FBGA CSR# inputs are HIGH. If either DCS# or CSR# input is LOW, the Qn outputs will function normally. The RESET# input has priority over the DCS# and CSR# control and will force the outputs LOW. If the DCS#-control functionality is not desired, the CSR# input can be hardwired to ground, in which case the set-up time requirement for DCS# would be the same as for the other D data inputs. The device supports low-power standby operation. When the reset input (RESET#) is LOW, the differential input receivers are disabled, and undriven (floating) data, clock, and reference voltage (VREF) inputs are allowed. In addition, when RESET# is LOW, all registers are reset and all outputs are forced LOW. The LVCMOS RESET# and Cn inputs must always be held at a valid logic HIGH or LOW level. To ensure defined outputs from the register before a stable clock has been supplied, RESET# must be held in the LOW state during power-up. In the DDR-II RDIMM application, RESET# is specified to be completely asynchronous with respect to CK and CK#. Therefore, no timing relationship can be guaranteed between the two. When entering reset, the register will be cleared and the outputs will be driven low quickly, relative to the time to disab……
