器件名称: CY2SSTU32864
功能描述: 1.8V, 25-bit (1:1) or 14-bit (1:2) JEDEC-Compliant Data Register
文件大小: 98.03KB 共9页
简 介:CY2SSTU32864
1.8V, 25-bit (1:1) or 14-bit (1:2) JEDEC-Compliant Data Register
Features
Operating frequency: DC to 500 MHz Supports DDRII SDRAM Two operations modes: 25 bit (1:1) and 14 bit (1:2) 1.8V operation Fully JEDEC-compliant (JESD82-7A) 96-ball FBGA The device monitors both DCS# and CSR# inputs and will gate the Qn outputs from changing states when both DCS# and CSR# inputs are high. If either DCS# or CSR# input is low, the Qn outputs will function normally. The RESET input has priority over the DCS# and CSR# control and will force the outputs low. If the DCS#-control functionality is not desired, the CSR# input can be hardwired to ground, in which case the set-up time requirement for DCS# would be the same as for the other D data inputs. The device supports low-power standby operation. When the reset input (RESET#) is low, the differential input receivers are disabled, and undriven (floating) data, clock, and reference voltage (VREF) inputs are allowed. In addition, when RESET# is low, all registers are reset and all outputs are forced low. The LVCMOS RESET# and Cn inputs must always be held at a valid logic high or low level. To ensure defined outputs from the register before a stable clock has been supplied, RESET# must be held in the low state during power-up. In the DDR-II RDIMM application, RESET# is specified to be completely asynchronous with respect to CK and CK#. Therefore, no timing relationship can be guaranteed between the two. When entering reset, t……
