器件名称: ASM5I9653A-32-LR
功能描述: 3.3V 1:8 LVCMOS PLL Clock Generator
文件大小: 648.99KB 共13页
简 介:July 2005 rev 0.2 3.3V 1:8 LVCMOS PLL Clock Generator
Features
1:8 PLL based low-voltage clock generator Supports zero-delay operation 3.3V power supply Generates clock signals up to 125MHz PLL guaranteed to lock down to 145MHz, output frequency = 36.25MHz Maximum output skew of 150 pS Differential LVPECL reference clock input External PLL feedback Drives up to 16 clock lines 32 lead LQFP & TQFP Packages Ambient temperature range 0°C to +70°C Pin and function compatible to the
ASM5I9653A
running at either 4x or 8x of the reference clock frequency. The ASM5I9653A is guaranteed to lock in a low power PLL mode in the high frequency range (VCO_SEL = 0) down to PLL = 145 MHz or Fref = 36.25MHz. The ASM5I9653A has a differential LVPECL reference input long with an external feedback input. The device is ideal for use as a zero delay, low skew fanout buffer. The device performance has been tuned and optimized for zero delay performance. The PLL_EN and BYPASS controls select the PLL bypass configuration for test and diagnosis. In this configuration, the selected input reference clock is bypassing the PLL and routed either to the output dividers or directly to the outputs. The PLL bypass configurations are fully static and the minimum clock frequency specification and all other PLL characteristics do not apply. The outputs can be disabled (high-impedance) and the device reset by asserting the MR/OE pin. Asserting MR/OE also causes the PLL to loose lock due to missing feed……
