器件名称: ASM2P3807AG-20-SR
功能描述: 3.3V CMOS 1-TO-10 CLOCK DRIVER
文件大小: 692.62KB 共19页
简 介:June 2005 rev 0.2
3.3V CMOS 1-TO-10 CLOCK DRIVER
Features
0.5 MICRON CMOS Technology Guaranteed low skew < 350pS (max.) Very low duty cycle distortion < 350pS (max.) High speed: propagation delay < 3nS (max.) Very low CMOS power levels TTL compatible inputs and outputs 1:10 fanout Maximum output rise and fall time < 1.5nS (max.) Low input capacitance: 4.5pF typical Operates with 3.3V ± 0.3V Supply Inputs can be driven from 3.3V or 5V components Available in SSOP, SOIC, and QSOP Packages
ASM2P3807AH
Product Description
The ASM2P3807AH 3.3V clock driver is built using advanced dual metal CMOS technology. This low skew clock driver offers 1:10 fanout. The large fanout from a single input reduces loading on the preceding driver and provides an efficient clock distribution network. The ASM2P3807AH offers low capacitance inputs with hysteresis for improved noise margins. Multiple power and grounds reduce noise. Typical applications are clock and signal distribution.
Block Diagram
O1 O2 O3 O4 O5 IN O6 O7 O8 O9
O10
Alliance Semiconductor 2575, Augustine Drive Santa Clara, CA Tel: 408.855.4900 Fax: 408.855.4999 www.alsc.com
Notice: The information in this document is subject to change without notice.
June 2005 rev 0.2
Pin Configuration
IN GND O1 VCC O2 GND O3 VCC O4 GND 1 2 3 4 5 6 7 8 9 10 20 VCC O10 O9 GND O8 VCC O7 GND O6 O5
ASM2P3807AH
A S M 2 P 3 8 0 7 A H
19 18 17 16 15 14 13 12 11
SOIC / SSOP/ QSOP Packages TOP VIEW
Pin Description Pin#
1 3,5,7,9,11……
