器件名称: ASM2P20807A-20-AT
功能描述: 2.5V CMOS 1-TO-10 CLOCK DRIVER
文件大小: 467.08KB 共11页
简 介:June 2005 rev 0.2 2.5V CMOS 1-TO-10 CLOCK DRIVER
Features
High frequency > 150MHz Guaranteed low skew < 150pS (max.) between any two outputs Very low duty cycle distortion < 300pS High speed: propagation delay < 3nS Very low CMOS power levels TTL compatible inputs and outputs 1:10 fanout Maximum output rise and fall time < 1.25nS (max.) Low input capacitance: 3pF (typ) 2.5V Supply Voltage Available in SSOP and QSOP Packages
ASM2P20807A
Product Description
The ASM2P20807A is a 2.5V compatible, high speed, low noise, 1:10 fanout, non-inverting clock buffer. The large fanout from a single input reduces loading on the preceding driver and provides an efficient clock distribution network. Providing output to output skew as low as 150pS, the ASM20807A is an ideal clock distribution device for synchronous systems. Multiple power and grounds reduce noise. Typical applications are clock and signal distribution.
Block Diagram
O1 O2 O3 O4 O5 IN O6 O7 O8 O9
O10
Alliance Semiconductor 2575, Augustine Drive Santa Clara, CA Tel: 408.855.4900 Fax: 408.855.4999 www.alsc.com
Notice: The information in this document is subject to change without notice.
June 2005 rev 0.2
Pin Configuration
IN GND O1 VCC O2 GND O3 VCC O4 GND 1 2 3 4 5 6 7 8 9 10 SSOP/ QSOP PACKAGE TOP VIEW 20 VCC O10 O9 GND O8 VCC O7 GND 06 O5
ASM2P20807A
A S M 2 P 2 0 8 0 7 A
19 18 17 16 15 14 13 12 11
Pin Description Pin #
1 3,5,7,9,11,12,14,16,18,19 2,6,10,13,17 4,8,15,20
Pin Names
IN O1-O10 GND VCC
……
