器件名称: ASM2I3805DG-20-DT
功能描述: 3.3V CMOS Dual 1-To-5 Clock Driver
文件大小: 500.97KB 共12页
简 介:June 2005 rev 0.2 3.3V CMOS Dual 1-To-5 Clock Driver
Features
Advanced CMOS Technology Guaranteed low skew < 200pS (max) Very low propagation delay < 2.5nS (max) Very low duty cycle distortion < 270pS (max) Very low CMOS power levels Operating frequency up to 166MHz TTL compatible inputs and outputs Inputs can be driven from 3.3V or 5V components Two independent output banks with 3-state control 1:5 fanout per bank ASM2P3805X Where X =D for 133MHz Operation X =E for 166MHz Operation "Heartbeat" monitor output VCC = 3.3V ± 0.3V Available in SSOP and QSOP Packages
ASM2P3805X
Functional Description
The ASM2P3805X is a 3.3V clock driver built using advanced CMOS technology. The device consists of two banks of drivers, each with a 1:5 fanout and its own output enable control. The device has a "heartbeat" monitor for diagnostics and PLL driving. The MON output is identical to all other outputs and complies with the output specifications in this document. The ASM2P3805X offers low capacitance inputs. The ASM2P3805X is designed for high speed clock distribution where signal quality and skew are critical. The ASM2P3805X also allows single point-to-point transmission line driving in applications such as address distribution, where one signal must be distributed to multiple receivers with low skew and high signal quality.
Pin Diagram
Block Diagram
OEA INA 5 OA1 – OA5
VCCA OA1 OA2 OA3 GNDA
1 2 3 4 5 6 7 8 9 10
20
VCCB OB1 OB2 OB3 GNDB OB4 OB5 MON OEB INB
INB OEB
……