器件名称: Z16C3220VSC
功能描述: IUSC
文件大小: 415.73KB 共121页
简 介:ZILOG
P R E L I M I N A R Y
Z16C32 IUSC
PRELIMINARY PRODUCT SPECIFICATION
Z16C32
IUSC INTEGRATED UNIVERSAL SERIAL CONTROLLER
FEATURES
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Two Full-Capacity 20 MHz DMA Channels, Each with 32-Bit Addressing and 16-Bit Data Transfers. DMA Modes Include Single Buffer, Pipelined, ArrayChained and Linked-Array Chained. Ring Buffer Feature Supports Circular Queue of Buffers in Memory. Linked Frame Status Transfer Feature Writes Status Information for Received Frames and Reads Control Information for Transmit Frames to the DMA Channel’s Array or Linked List to Significantly Simplify Processing Frame Status and Control Information. Programmable Throttling of DMA Bus Occupancy in Burst Mode with Bus Occupancy Time Limitation. 0 to 20 Mbit/sec, Full-Duplex Channel, with Two Baud Rate Generators and a Digital Phase-Locked Loop for Clock Recovery. 32-Byte Data FIFOs for Receiver and Transmitter Up to 12.5 MByte/sec (16-Bit) Data Bus Bandwidth
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HDLC/SDLC Mode with 8-Bit Address Compare; Extended Address Field Option; 16- or 32-Bit CRC; Programmable Idle Line Condition; Optional Preamble Transmission and Loop Mode. Selectable Number of Flags Between Back-to-Back Frames. Byte Oriented Synchronous Mode with One-to-Eight Bits/Character; Programmable Sync and Idle Line Conditions; Optional Receive Sync Stripping; Optional Preamble Transmission; 16- or 32-Bit CRC; Transmitto-Receive Slaving (for X.21). External Character Sync Mode for Receive Transparent Bisync Mode with EBCDIC or ASCII……
