器件名称: W3EG64255MS100JD3GG
功能描述: 2GB - 2x128Mx64 DDR SDRAM REGISTERED, w/PLL
文件大小: 203.35KB 共13页
简 介:White Electronic Designs
W3EG64255S-JD3
ADVANCED*
2GB – 2x128Mx64 DDR SDRAM REGISTERED, w/PLL
FEATURES
Double-data-rate architecture DDR200, DDR266 and DDR333; JEDEC design specications Bi-directional data strobes (DQS) Differential clock inputs (CK & CK#) Programmable Read Latency 2,2.5 (clock) Programmable Burst Length (2,4,8) Programmable Burst type (sequential & interleave) Edge aligned data output, center aligned data input. Auto and self refresh Serial presence detect Dual Rank Power supply: VCC 2.5V ± 0.2V JEDEC standard 184 pin DIMM package JD3: 30.48 (1.20")
NOTE: Consult factory for availability of: RoHS compliant products Vendor source control options Industrial temperature option * This product is under development, is not qualied or characterized and is subject to change or cancellation without notice.
DESCRIPTION
The W3EG64255S is a 2x128Mx64 Double Data Rate SDRAM memory module based on 512Mb DDR SDRAM component. The module consists of sixteen 256Mx4 stacks, in 66 pin TSOP packages mounted on a 184 pin FR4 substrate. Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges and Burst Lengths allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.
OPERATING FREQUENCIES
DDR333 @CL=2.5 Clock Speed CL-tRCD-tRP 166MHz 2.5-3-3 DDR266 @CL=2 133MHz 2-2-2 DDR266 @CL=2 133MHz 2-3-3 DDR266 @CL=2.5 133MHz 2.5-3-3 DDR200 @CL=2 100MHz 2-2-2
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