器件名称: W532
功能描述: Frequency Multiplying, Peak Reducing EMI Solution
文件大小: 129.98KB 共8页
简 介:W532
Frequency Multiplying, Peak Reducing EMI Solution
Features
Cypress PREMIS family offering Generates an EMI optimized clocking signal at the output Selectable frequency range and multiplication factor Single 1.25% or 5% center spread output Integrated loop filter components Operates with a 3.3V or 5V supply Low power CMOS design Available in 16-pin SOIC Table 1. Output Frequency Range Selection OR2 0 0 1 1 OR1 0 1 0 1 Output Range (Multiplication Factor Selection) reserved 15 MHz ≤ FIN ≤ 30 MHz 30 MHz ≤ FIN ≤ 60 MHz 60 MHz ≤ FIN ≤ 120 MHz
Table 2. Modulation Width Selection MW 0 1 Output Favg + 0.625% ≥ Fout ≥ Favg – 0.625% Favg + 2.5% ≥ Fout ≥ Favg – 2.5%
Key Specifications
Supply Voltages: ........................................VDD = 3.3V ±0.3V or VDD = 5V ±10% Frequency Range: .........................15 MHz ≤ Fout ≤ 120 MHz Cycle to Cycle Jitter: ......................................... 150 ps (typ.) Output Duty Cycle: ............................... 40/60% (worst case) Output Rise and Fall Time ................................... 5 ns (max.)
Table 3. Input Frequency Range Selection IR2 0 0 1 1 IR1 0 1 0 1 Input Range reserved 15 MHz ≤ FIN ≤ 30 MHz 30 MHz ≤ FIN ≤ 60 MHz 60 MHz ≤ FIN ≤ 120 MHz
Simplified Block Diagram
3.3V or 5.0V
Pin Configuration
SOIC
X1 XTAL Input X2
W532
Spread Spectrum Output (EMI suppressed)
X1 X2 AVDD *OR1 NC AGND ^OR2 *SSON#
1 2 3 4 5 6
16 15 14 13 12 11 10 9
VDD GND IR1^ IR2^ SSOUT GND VDD MW*
W532
7
8
3.3V or 5.0V
O……
