器件名称: W3H32M72E-400SBC
功能描述: 32M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package
文件大小: 920.11KB 共30页
简 介:White Electronic Designs
W3H32M72E-XSBX
PRELIMINARY*
32M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package
FEATURES
Data rate = 667*, 533, 400 Package: 208 Plastic Ball Grid Array (PBGA), 18 x 20mm 1.0mm pitch Differential data strobe (DQS, DQS#) per byte Internal, pipelined, double data rate architecture 4-bit prefetch architecture DLL for alignment of DQ and DQS transitions with clock signal Four internal banks for concurrent operation (Per DDR2 SDRAM Die) Programmable Burst lengths: 4 or 8 Auto Refresh and Self Refresh Modes On Die Termination (ODT) Adjustable data – output drive strength Single 1.8V ±0.1V supply Programmable CAS latency: 3, 4, 5, or 6 Posted CAS additive latency: 0, 1, 2, 3 or 4 Write latency = Read latency - 1* tCK Commercial, Industrial and Military Temperature Ranges Organized as 32M x 72 Weight: W3H32M72E-XSBX - 2.5 grams typical
BENEFITS
65% SPACE SAVINGS vs. FPBGA Reduced part count 54% I/O reduction vs FPBGA Reduced trace lengths for lower parasitic capacitance Suitable for hi-reliability applications Upgradable to 64M x 72 density (contact factory for information)
* This product is under development, is not qualied or characterized and is subject to change without notice.
FIGURE 1 – DENSITY COMPARISONS Actual Size W3H32M72E-XSBX
11.0
CSP Approach (mm)
11.0 11.0 11.0 11.0
20 19.0 90 FBGA 90 FBGA 90 FBGA 90 FBGA 90 FBGA
White Electronic Designs W3H32M72E-XSBX
18
S A V I N G S
65% 54%
Area I/O Count
5 x 209mm2 = 1,045mm2 5 x 90 balls = 450 ball……
