器件名称: W3E64M72S-333BC
功能描述: 64Mx72 DDR SDRAM
文件大小: 674.19KB 共19页
简 介:White Electronic Designs
64Mx72 DDR SDRAM
FEATURES
Data rate = 200, 250, 266 and 333Mbs Package: 219 Plastic Ball Grid Array (PBGA), 25 x 32mm 2.5V ±0.2V core power supply 2.5V I/O (SSTL_2 compatible) Differential clock inputs (CK and CK#) Commands entered on each positive CK edge Internal pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle Programmable Burst length: 2,4 or 8 Bidirectional data strobe (DQS) transmitted/ received with data, i.e., source-synchronous data capture (one per byte) DQS edge-aligned with data for READs; centeraligned with data for WRITEs DLL to align DQ and DQS transitions with CK Four internal banks for concurrent operation Data mask (DM) pins for masking write data (one per byte) Programmable IOL/IOH option Auto precharge option Auto Refresh and Self Refresh Modes Commercial, Industrial and Military TemperatureRanges Organized as 64M x 72 Weight: W3E64M72S-XBX - 4.5 grams typical
W3E64M72S-XBX
ADVANCED*
BENEFITS
66% Space Savings vs. TSOP Reduced part count 55% I/O reduction vs TSOP Reduced trace lengths for lower parasitic capacitance Suitable for hi-reliability applications Laminate interposer for optimum TCE match
GENERAL DESCRIPTION
The 512MByte (4Gb) DDR SDRAM is a high-speed CMOS, dynamic random-access, memory using 9 chips containing 536,870,912 bits. Each chip is internally configured as a quad-bank DRAM. The 512MB DDR SDRAM uses a double data rate ar chi tec ture to achieve high-speed operation. The double ……
